In structures of semiconductor-on-insulator (SeOI) type, a buried dielectric layer electrically insulates the semiconductor layer from the support substrate.
In the case where the material of the dielectric layer is silicon dioxide (SiO2), the buried dielectric layer is generally denoted by the acronym BOX of the term “Buried OXide.”
In partially depleted (PD) SeOI structures, the thickness of the buried dielectric layer is generally greater than 100 nm and is, thus, sufficient to ensure the electrical integrity and the quality of the layer. The thickness of the semiconductor layer is then typically between 100 nm and 200 nm.
On the other hand, in fully depleted (FD) SeOI structures, the semiconductor layer has an ultrathin thickness, that is to say, of less than or equal to 50 nm, typically of the order of 12 nm and which may be reduced down to around 5 nm. In order to benefit from the proven advantages of the rear face polarization of the channel, the thickness of the buried dielectric layer may also be reduced, by a typical thickness of the order of 150 nm, down to values of less than 50 nm, typically 25 nm, and which may drop down to 5 nm.
Such structures are in particular intended for the manufacture of transistors, the channel layer being formed in or on the ultrathin semiconductor layer, which is not doped.
Owing to the ultrathin thickness of the buried dielectric layer and of the semiconductor layer, these FD SeOI structures have the advantage of enabling a precise control of the channel of the transistor, of improving the short channel effect and of reducing the variability of the transistor.
For FD SeOI transistors, the total variability results from the gate line edge roughness (LER) from the variability of the work function and from the thickness of the channel.
In so far as the channel is not doped, the total variability is not subjected to random dopant fluctuation (RDF).
Consequently, the uniformity of the thickness of the semiconductor layer forming the channel is an important parameter for limiting the variability of an FD SeOI device.
In this regard, the specifications include both an “intra-wafer” uniformity (that is to say, on the surface of one and the same structure, the structure generally being in the form of a circular wafer) and a “wafer-to-wafer” uniformity (that is to say, between all of the structures belonging to all of the production batches).
The combination of these two uniformity conditions is denoted by the expression layer total thickness variability (LTTV), and influences the parameters of the process for manufacturing FD SeOI structures in order to obtain the desired uniformity.
Thus, for FD SeOI applications, a total thickness variability of the semiconductor layer of the order of ±0.5 nm is targeted, preferably with the order of ±0.2 nm wafer-to-wafer, that is to say, between the various structures resulting from all of the production batches.
International Patent Publication WO 2004/015759 relates to a process for correcting the thickness of the semiconductor layer of an SeOI structure based on a selective sacrificial oxidation of the layer.
Depending on the processing conditions, the sacrificial oxidation consumes a greater or lesser thickness of the semiconductor layer.
The sacrificial oxide layer is then removed by selective etching, typically using hydrofluoric acid (HF).
However, the structures that are the subject of this process are not only FD SeOI structures but “conventional” PD SeOI structures.
Furthermore, the order of magnitude of the accuracy of the thinning obtained by the sacrificial oxidation in equipment of “batch” type, that is to say, equipment (for example, an oven) in which a plurality of structures are treated simultaneously, is greater than the accuracy according to which it is desired to control the uniformity on an FD SeOI structure.
Indeed, since the temperature is not completely uniform in the equipment, the oxidized thickness may vary within one and the same structure and/or from one structure to the next.
Thus, at the end of such a thinning operation, a variation of ±1 nm to 1.5 nm on average of the thickness of the semiconductor layer is obtained.
FIG. 1 illustrates the distribution of the mean thickness emean compared to a target thickness et of the semiconductor layer that may be obtained at the end of a sacrificial oxidation process as described above and as applied to the manufacture of PD SeOIs.
It is, therefore, necessary to define a process for controlling the mean thickness of the semiconductor layer that is particularly adapted to the accuracy desired for the layers of FD SeOI structures.
One objective of the invention is, therefore, to provide a process for treating structures of semiconductor-on-insulator type for “fully depleted” applications that make it possible to standardize the thickness of the semiconductor layer between various structures over the whole of a production volume (wafer-to-wafer thickness).
Such a process must be able to be implemented on an industrial scale by modifying as little as possible of the existing SeOI manufacturing processes.
The process must also be able to be carried out with commercially available and inexpensive means.
Another objective of the invention is to provide a process for manufacturing structures of semiconductor-on-insulator type that makes it possible to guarantee a good uniformity of the structures produced.